Hello, We are working on 8051 project; Presently we are using code banking. our code size are around 80K We wanted to use XDATA banking together with code banking on the same project; 128K SRAM we selected; can we do? i seen the thread >>http://www.keil.com/forum/docs/thread1524.asp 1. if 8051 support the 64K code & data; why 32K bank is required; can we use 64K code and 64K data banking; 2. In our project we are using 128K eprom & 128K SRAM; can we connect the same extra pin for both the chips; or each chip required separate pins of micro controller. 3. why 32K page required in XDATA Banking? As seen the semiconductors manufacture >> no one manufacture of 64K SRAM; only 32K , 128K and more; how many banks we may use in our project. 4. difference between BL51 & LX51, which linker we should use.
1. When you have no common area, the compiler must perform for each memory access a bank switch (to make sure that the correct bank is selected). This may become very in-efficient. Therefore we *STRONGLY* recommend to implement a common area in an classic 8051 design. 2. + 3. see http://www.keil.com/support/man/docs/lx51/lx51_bk_example4.htm for an example configuration. Just ignore A17. 4. http://www.keil.com/c51/lx51.asp. For XDATA Banking you need Far Memory Support that is only available with LX51.
XDATA banking may be totally unnecessary. I have an app with 2MByte of XDATA and using XDATA banking is prohibitive because of the overhead. Now, it turns out that 64k of XDATA is enough 99.999% of the time and the solution is to drop XDATA banking and have a function U8 ReadHighData(U16 addr). That way the whole thing run full speed 99.999% of the time and the overhead averages out to be 2 orders of magnitude less than with banking Erik