I have a thought that would make many processes much more effective and, being only one voice, I would like to know if there is a demand before I propose it to Keil. This is the result of me having to change a switch statement to a series of IFs to make an ISR process fast enough. I realize, and thus do not complain, that Keil caould not implemet an ANSI-C switch more efficient than the way it is done. 'n' below will be either 2 or 3 (if Keil decide to implement, they can choose) a Proposal: if #pragma QUICKSWITCH then a) no case value can be more than 255 b) all case values must be multiples of n c) the switch will be implemented as a jump table Erik
getting late, I now see the 'return', I included it to the below and ?C?CCase is still called. what is different from what you show?
367 //////////////////////////////////////////////////////////// 368 // 369 // ISR 14: void ISR_T3 (void) 370 // 371 372 void ISR_T3 (void) interrupt 14 using 1 373 { 374 1 SB1_TMR3CN_TR = 0; 375 1 SB1_TMR3CN_TF = 0; 376 1 switch (GC4holdState) 377 1 { 378 2 case G4HS_IDLE: // 0x00 should never happem 379 2 catchT3(0x01); 380 2 // break; 381 2 return; 382 2 383 2 case G4HS_RCDN: // 0x01 receive complted now processing 384 2 SBG_P0_D485 = 1; 385 2 SG_SFRPAGE = 0; 386 2 SB0_SCON0_TB8 = 1; 387 2 S0_SBUF0 = RSP_BUSY; 388 2 // break; 389 2 return; 390 2 391 2 case G4HS_RCCM: // 0x02 processing of receive complted 392 2 SBG_P0_D485 = 1; 393 2 SG_SFRPAGE = 0; 394 2 SB0_SCON0_TB8 = 1; 395 2 S0_SBUF0 = RSP_CMPL; 396 2 GC4holdState = G4HS_RCHO; 397 2 // break; 398 2 return; 399 2 400 2 case G4HS_RCER: // 0x03 receive complted, error detected, record ignored 401 2 SBG_P0_D485 = 1; 402 2 SG_SFRPAGE = 0; 403 2 SB0_SCON0_TB8 = 1; 404 2 S0_SBUF0 = RSP_ERR; 405 2 GC4holdState = G4HS_RCHO; 406 2 // break; 407 2 return; 408 2 409 2 case G4HS_RCHO: // 0x04 receive response completed hold off switch to receive 410 2 SBG_P0_D485 = 0; // now back to receive 411 2 GC4holdState = G4HS_IDLE; // no response cycle in progress 412 2 GCI4xferSt = I4_IDLE; // new interrupt sequence 413 2 // break; 414 2 return; 415 2 416 2 // default: 417 2 // catchT3(0xff); 418 2 // break; 419 2 420 2 } 421 1 } ; FUNCTION ISR_T3 (BEGIN) 0000 C0E0 PUSH ACC 0002 C083 PUSH DPH 0004 C082 PUSH DPL 0006 C0D0 PUSH PSW 0008 75D008 MOV PSW,#08H ; SOURCE LINE # 372 ; SOURCE LINE # 374 000B C2CA CLR SB1_TMR3CN_TR ; SOURCE LINE # 375 000D C2CF CLR SB1_TMR3CN_TF ; SOURCE LINE # 376 000F E500 E MOV A,GC4holdState 0011 120000 E LCALL ?C?CCASE