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NAND FAT file system management

Hello experts,

I am developing a C165 based mass storage device and need to implement a FAT file system on flash.

I've read a lot about problems with the life time of NAND due to repeated read/write of the FAT and ST talk about wear levelling software and journeling which are basically jump tables relating vitual addresses to physical addresses to combat the problem.

I know that there are commerical file systems offered by companies and would really like to know if anyone has experience of any of these or selecting NAND for this purpose.

All advice and links greatly appreciated,

Best regards,

Malcom.

Parents
  • Hello again,

    Thanks again for your thoughts. My logger files are about 900Kb and I will need to write several files each day. The 4Mb requirement comes from needing several days worth of files stored.

    I've got 2 options:-

    1. Use on-board SRAM (approx 40Kb) to buffer data which can then be written to flash in chunks.

    2. Use battery backed SRAM. Which I've looked for but failed to find in large (~4Mb) densitys using serial protocals.

    Would be very grateful if your friend could recommend a large serial SRAM. Think this would be the best solution.

    Best regards,

    Malcom

Reply
  • Hello again,

    Thanks again for your thoughts. My logger files are about 900Kb and I will need to write several files each day. The 4Mb requirement comes from needing several days worth of files stored.

    I've got 2 options:-

    1. Use on-board SRAM (approx 40Kb) to buffer data which can then be written to flash in chunks.

    2. Use battery backed SRAM. Which I've looked for but failed to find in large (~4Mb) densitys using serial protocals.

    Would be very grateful if your friend could recommend a large serial SRAM. Think this would be the best solution.

    Best regards,

    Malcom

Children
  • Malcom;
    Once again I was in error. My friend had the same problems trying to locate a large serial SRAM. He uses the Maxim-IC DS1270W as an on chip battery backed SRAM. It has parallel access.
    For his 12Mbyte Flash, he uses the SST25LF080 4 wire SPI device. It is an 8Mbit device arranged as 1Mbyte x 8. He plans to use the SSTVL160 device as 2Mbyte x 8. It has the same footprint but was not available for his prototype.
    Both types have small page size so erasures are reduced.
    His datalogging device is a slave to a larger system. For rapid access, he saves data in the SRAM. If not accessed in X time he then writes to Flash for long time storage. Once again he writes smaller blocks to sequential pages as a circular que. He erases only when he needs to overwrite an old block of data.

  • Hello again Al,

    Thanks for the info.

    I've found a 16Mb SPI flash and will do exactley the same thing.

    Cheers,

    Malcom