I meet a question: I want to make a hardware emulator do to some experiment with mcs-51 microcomputer!But i am not very clear understand the thoery of the emulator! I use a device with 64k FALSH ROM on-chip.it can well connect with the keil debugger!but i don't know where my application code stores! thank you for your help first!
xu, What chip are you using? That will probably make a big difference as to knowing where and how it connects with the debugger. Does the chip have JTAG hardware?
"Does the chip have JTAG hardware?" Note that JTAG is just the interface; you need both the JTAG interface and the on-chip Debug hardware ro give you the "built-in ICE" (Some chips - eg, some uPSDs - have a JTAG interface just for flash-programming but with no on-chip debug)
Andy, I'm plenty familiar with that. I designed-in a uPSD3254 processor to my latest project JUST before they released the uPSD33XX series with boundary scan functionality. As such, I had to go the more expensive ICE route. It's my understanding that the majority of chips that include a JTAG interface also include the on-chip debug functionality, though. Is that generally the case?
"It's my understanding that the majority of chips that include a JTAG interface also include the on-chip debug functionality, though. Is that generally the case?" I think so. But, as you obviously know, it ain't necessarily so...! Some chips have JTAG but no on-chip debug (eg, the uPSDs mentioned earlier); some chips have on-chip debug, but no JTAG (they use some other proprietary interface).
I guess that you are designing an 8051 device. You may use either the ISD51 or FlashMonitor within your device. Another way is that you build a debugger peripheral on silicon and then use the AGDI interface(http://www.keil.com/appnotes/docs/apnt_145.asp) to connect it with the uVision Debugger.
Thank you very much for your help!the details information about the emulator I want to know clearly is that :the cpu is SST89E554 with 32k external RAM mapped 8000h-ffffh and von Neumam linked!I have understand that the chip have SoftICE in it!But I am not how my application code works!
Xu, It's required for 3 memory segments for your Mon51 application. One for 4~5Kbytes as mon51 code memory(ROM). One banked (or not ) Von.Nuemam linked ram for your application code. One for your application data. When reset, mon51 takes control on your board. PC is pointed to mon51 code memory, the Von.Nuemam memory act as data memory at this time. Mon51 communicates with keil and download your application code into that memory area. the variables for mon51 is also stored in this area. Mon51 write with 'WR' and read with'RD'. Your application data area is out of the Mon51 control. When you start up your application program, your own code takes control on your board. It simply runs as started from reset and do not "know" Mon51 runs previously. Now the application data area is available for your code. The Von.Nuemam area is sampled by PSEN as program code. So you must connect RD & PSEN with a AND gate together, to RD on Von.Nuemam ram. Relocate your interrupt segment and code, xdata segment when you linked up your application program.