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80C390 Chip Enables and Contiguous Addressing mode

Hello,


Thanks for all that posted regarding this previously, however I am still having trouble getting this to work. I have a PCB with a DS80C390 and a UART which is enabled/disabled via the ~CE1 signal (Pin 33) on the 80C390.

Is there anyway that I can leave the 80C390 in the 16-Bit Standard 8051 addressing mode and still be able to have the 80C390 decode the address lines to internally decode the Chip Enable signals????

For example, I set the Port 4 Control Register to enable ~CE0 and ~CE1 and also set P4.4 to be used as A16. I have also set the MCON register to allow ~CE0 and ~CE1 to be used for both Program/Data memory (thus ~CE0 should be asserted for xdata memory accesses in 0h-1FFFFh and ~CE1 should be asserted for 20000h-3FFFFh.) I am trying to access the registers of the UART with the following lines in my code:

while(1)
{
temp = *((unsigned char xdata *)0x02C000);
temp = *((unsigned char xdata *)0x02B000);
temp = *((unsigned char xdata *)0x02A000);
__WATCHDOG_RESET;
}

When I use a scope to check the signals, I see that ~CE0 is getting asserted instead of ~CE1. I read some Application notes that mentioned changing the Target and Device settings in uVision2 for contiguous mode and using the LX51 and AX51 to link and assemble the files. However, is it safe to change the memory model and Code Rom Size in the middle of a project?? Also, I don't have the ax51 and lx51 assembler and linker.

Is there a way that the 80C390 can decode the Chip Enables in the Standard 16-Bit Addressing mode?? Or is required to change the Device and Target Settings to use LX51, AX51, and coniguous mode in order to achieve this????

I am new to 8051 and would greatly appreciate any help.

Thanks,

A.R.

Parents
  • Please don't start a new thread from scratch to continue a discussion that has been started in an existing one.

    Without turning on continuous mode, the C390 won't even recognize that > 64 KiB addresses exist, much less handle them automatically. You have to either wiggle the PCE/CE lines yourself (assisted by Keils's XRAM paging support), or turn on continuous mode.

Reply
  • Please don't start a new thread from scratch to continue a discussion that has been started in an existing one.

    Without turning on continuous mode, the C390 won't even recognize that > 64 KiB addresses exist, much less handle them automatically. You have to either wiggle the PCE/CE lines yourself (assisted by Keils's XRAM paging support), or turn on continuous mode.

Children
  • Thanks for the reply Hans.

    I have the DK51, so I guess using contiguous mode is out of the question for now.

    What is Keil's XRAM paging support?? I haven't been able to find any references or examples for this. Is it the same as the 22-bit paged address mode for the 80C390?? As far as I understand, the paged mode works on using the lower 8 address bits for 256 byte addressing and the upper 8 bits for paging, but how I can use this to wiggle the CE1 pin manually??

    I could assert the CE1 pin every time before accessing the UART's registers, and the de-assert it right after. But this would seem to be adding too much code and affect the performance of the controller.

    Any suggestions?? I appreciate your help and time.

    Thanks,

    A. Rawat

  • Large Memory Support (XBANKING) and Large Chip Support (i.e. Philips 80C51MX + Dallas contiguous mode) require the PK51 Professional Developers Kit.

    See also: http://www.keil.com/c51/.

  • I could assert the CE1 pin every time before accessing the UART's registers, and the de-assert it right after.

    Yes, that's exactly what you'll have to do.

    But this would seem to be adding too much code and affect the performance of the controller.

    Well, you made that hardware design decision, and you made the decision not to use PK51 --- now you have to live with the consequences, or to review and change your hardware or your tools. It's eventually as simple as that.