There are two interrupts pertinent to the FIFO Rx buffer (only concerned with Rx for now): one to indicate the number of trigger bytes have been Rx'd - I've set this to 1(one); the other is when there is a minimun of one char in the Rx buffer but no char has Rx'd by or read from buffer during a time interval of approx. 4 char times. 'IF' I understand the documentation correctly, the 'no activity w/ char pending' interrupt is used for cases where there are not enough chars in the buffer to trigger a level interrupt - allowing for servicing any 'left-over' bytes. If this is true, and the trigger level is set to one - am I safe to assume that if there are multiple bytes in the Rx FIFO and I service the first one, an interrupt will be generated immediately following the resetting/re-enable of interrupts in that ISR (reading U0IIR and settting VICVectAddr = 0)??? I am asking this to know for certain that the above understanding/assumption is correct. If its not then it would seem that I would be reduced to 1/4 of my desired BAUD for the remaining chars which would not be acceptable. Basically I'm just asking if the FIFO trigger level is set to 1 (one) will a RDA/trigger level interrupt be generated for every char in the buffer? -m
first off, I should apologize for not stating which processor I am using - LPC2129 and also this should have been listed as pertaining to the ARM toolset. I am answering my own question here (which was answered by Philips support) in case someone else searches for this information. When the FIFO trigger level is set to 1, an interrupt is triggered for every byte in the FIFO - the time triggered interrupt is only for higher levels.