as the title.
Some variants use the 0xEA (IIRC) instruction as a "Trap" - eg, the Triscend E5 uses it as a software breakpoint.
My memory was incorrect: the instruction is 0xA5.
The only 'wrong' instruction is the 0xA5 instruction, which has different behaviors on different processors. Check out http://www.8052.com/51und.phtml for more information.
Thanks! Stoic