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I am recently changed to Infineon C164 - 8EM DA revision chip (64K OTP ROM) in standalone mode (EA pin high). The CA revision has always worked fine in standalone with exactly the same sw code. When changing to to newer DA verion The software runs eight time slower (i.e. instead of the external 5 MHz clock multiplied by 4 it divides it by two!). I've updated to the latest startup.a66 (extended architure) code with programs the syscon 2 registers and should take care of CLKCFG for clock PLL generation. But no matter what I do the chip seems to runs at 2.5 Mhz. Surely other people have used the DA chip ok?
Late but now we also have got to change from CA to DA step. did you already solve your problem? If yes, can you tell me how?
Hello Juergen, I received your email, don't worry, you're welcome... The DA step implements a new feature that allows the designer to omit configuration resistors on P0 when the chip is started in Single Chip Mode (EA = 1). The chip starts at the slowest possible PLL clock multiplication, this means CLK/2; the user must write in the RSTCON register the proper startup configuration, as if it were read from P0 during reset. Here is how we modified our START167.A66 file.
?C_RESET PROC TASK C_STARTUP INTNO RESET = 0 ?C_STARTUP: LABEL Model $IF (WATCHDOG = 0) DISWDT ; Disable watchdog timer $ENDIF ;This is the RSTCON value for OUR hardware, ;just write the proper configuration for yours MOV R15,#09B00H NOP NOP MOV RSTCON,R15 NOP NOP EXTR #1 MOV SYSCON2,#00500H NOP NOP EXTR #1 MOV SYSCON2,#00400H BCON0L SET (_MTTC0 << 5) OR (_RWDC0 << 4)
Hello Bruno I am a colleague from Juergen. Another question: How could you define the RSTCON register. Cause it is not a SFR register And the following code line does not work with the keil compiler >>> RSTCON DEFR 0FE10H <<<< Why do you use the NOP lines (a matter of speed?) best regards Reinhard
The current header files contain the correct definition for this SFR. It is a standard C pointer construct:
#define RSTCON (*((unsigned int volatile sdata *) 0xF1E0)) // Reset Control Register
Hello Juergen, I answer to your last e-mail on the forum, so maybe other users can benefit of this. At 08.07 16/06/2004 +0200, you wrote: Hello Mr. Coppi, thanks for your quick reply, the "some times" connect at low baud rates is our experience too so if you commit that it's not a problem of our system it's a feature. I will implement the code for setting of the RSTCON register, thanks again. what kind of tools do you use to program the OTP? what we detected this morning, it's possible to place a external memory modul on our system to disable the OTP and run code from external flash or SRAM (depends on modul). this dosen't work any more. the processor dosent start. debuging with keil monitor/debugger is not possible also (very usefull when placing the SRAM modul on the system). did they elliminate the whole P0 configuration mechanism? how does the C164 handle the external memory after reset? have you got any experience to? kind regards from rainy Austria, Juergen Read carefully the new manual, the P0 configuration does not work anymore, you should use RSTCON. If you use the Bootstrap to load Keil Monitor, you must modify the Keil Boot Loader in order to reconfigure RSTCON, just the same way as you modified the Startup code. Put into the bootloader code the same sequence I gave you in my first reply, and everything will work again. By the way, we still use Memtool to program C164, I already informed Infineon about the low baudrate problem, I hope they will fix the timeout problem quickly. To answer last Reinhard question, I don't remember why we put the NOPs inside the startup sequence, maybe due to a pipeline problem, then the system worked and we never touched it again...
Sorry, I forgot to mention that P0 configuration is NOT working when you reset the chip with EA = 1 or during Bootstrap. If EA = 0 at reset, you still must know how to drive the external bus, so P0 must provide the correct info. Anyway, please refer to the C164 manual. Ciao Bruno
Please try Memtool 3.3.1. Regards, Ursula Kelling