Long Question for coding suggestions

Hello,
FIrstly your website is great. I just like know if you can advice some thing about the following;

1) when controller starts , it starts scanning P2.0 , waiting for a HIGH Signal to come (JB p2.0,$),nothing happens untill high comes on P2.0.

2) As soon as High Comes on P2.0 , controller sents eight bit data from P1 to a device (MT8816 analog switch) and starts a 5 - Second Counter.
P1 - 0001001B

3) Now controller checks if LOW comes within 5-seconds check then controller sents a data or if no LOW comes within 5 -seconds then also controller sents data to P1 disconnecting the switch that was connected when HIGH came. And after this again takes the bit P2.0 for scanning.
P1 - 00001000B

Now please suggest how to write the code for this considering that later 8 bits will come and there has to be scanning of P2.0 to P2.7 and each bit has two types of data for HIgh and low state and 5-seconds counter.

How to do this multi-tasking please explain only for one bit.

for this i got a code from some one through email but unable to understand few thing can you please explain these.. by writing comments in front of the code.


; some global variables
BITS_STATUS EQU 0x20 ; bits' process statuses
; delay counters
BIT0_DELAY EQU 0x21
BIT1_DELAY EQU 0x22
BIT2_DELAY EQU 0x23
BIT3_DELAY EQU 0x24
BIT4_DELAY EQU 0x25
BIT5_DELAY EQU 0x26
BIT6_DELAY EQU 0x27
BIT7_DELAY EQU 0x28

START:
; initialize all delays to base scan values (BITx_DELAY)
; clear all bits' statuses (BITS_STATUS)
CALL INIT_BIT_PROC
;
MAIN_LOOP:
; wait for timer quanta (via timer or simple DJNZ loops for needed time)
CALL WAIT_QUANTA
;
MOV R7,#0 ; process bits from 0...
NEXT_BIT:
CALL PROCESS_BIT
INC R7
CJNE R7,#8,NEXT_BIT ; ...to 7
; ...

; bit processor
; R7 - bit number
PROCESS_BIT:
; locate corresponded structure
MOV DPTR,#BITS_LOOKUP
MOV A,R7
ADD A,R7
ADD A,DPL
MOV DPL,A
JNC PROCESS_BIT_0
INC DPH
PROCESS_BIT_0:
; get descriptor pointer into DPTR
MOV A,#1
MOVC A,@A+DPTR ; low byte of its address
PUSH ACC
CLR A
MOVC A,@A+DPTR ; high byte
MOV DPH,A
POP DPL
; now DPTR contains the address of bit process descriptor - let start to process
; a) check if delay done
MOV A,#1
MOVC A,@A+DPTR ; delay holder address
MOV R0,A
MOV A,@R0 ; delay value
DEC A
JZ PROCESS_BIT_1
; still need to wait:
MOV @R0,A
RET
PROCESS_BIT_1:
b) check real bit state in port
CLR A
MOVC A,@A+DPTR
MOV R1,A ; bit mask
ANL A,P2 ; check bit state in port
MOV C,P ; c is equ bit state
; c) process bit state depending on process status
MOV A,R1
ANL A,BITS_STATUS
JNZ PROCESS_BIT_R ; state: repeat_scan...
; state: initial_scan
JNC PROCESS_BIT_L ; low level detected...
; still in high state: reload initial scan delay
MOV @R0,#1 ; check bit again at next cycle
RET

PROCESS_BIT_L:
; first_low_state detected
; - change process status
MOV A,R1
ORL BITS_STATUS,A ; set status (repeat scan)
; - change delay value
MOV @R0,#DELAY_5_SEC ; depends on time quanta
; - send data byte via P1
MOV A,#2
MOVC A,@A+DPTR ; first_low_state
MOV P1,A
RET

PROCESS_BIT_R:
; state: repeat_scan
JNC PROCESS_BIT_H ; back-to-high level detected...
; continue_low_state detected:
; - keep delay value
MOV @R0,#DELAY_5_SEC
; - send data byte via P1
MOV A,#3
MOVC A,@A+DPTR ; continue_low_state
MOV P1,A
RET
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