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Can anybody help me to explain the following sequence ? I only had some expericence in coding x86 Assembly. #pragma asm CLR TR0 MOV A,#K_Timer0IntervalCompLo ADD A,TL0 MOV TL0,A MOV A,#K_Timer0IntervalCompHi ADDC A,TH0 MOV TH0,A NOP NOP NOP NOP SETB TR0 #pragma endasm Thanks. EricLin eric.yc.lin@liteon.com
These instructions stop 16-bit timer 0 to prevent its two 8-bit registers (TH0 and TL0) from changing while the MSB and LSB of a 16-bit "reload" constant (K_Timer0IntervalCompHi and K_Timer0IntervalCompLo) are added into that register pair. The NOPs presumably pad the timing out to match the reload, then the timer is started back up again.
"I only had some expericence in coding x86 Assembly." The principle is exactly the same, whatever the processor: you need to read 1. The Instruction Set Manual - to find out what each instruction means; 2. The processor architecture description - to find out what all the registers etc do. For the 8051, you will find all this (and more) in these documents: http://www.semiconductors.philips.com/acrobat/various/80C51_FAM_ARCH_1.pdf http://www.semiconductors.philips.com/acrobat/various/80C51_FAM_PROG_GUIDE_1.pdf http://www.semiconductors.philips.com/acrobat/various/80C51_FAM_HARDWARE_1.pdf
Thanks, Dan.
Thanks, Andy. I will save time for those docs.