What is the max bit rate of the SPI in the MSC1212Y3

I wonder which of the students I'm marking it was that wrote that....

The assignment was meant to be a learning exercise to teach them how to read datasheets, and find information.

Here's the marking comments just about all of them are getting.
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The chip does support synchronous serial communication. The table for the Serial Port 0 Control (SCON0) on page 38 of the MSC datasheet shows that mode 0 allows for synchronous communication on the serial port.

The maximum bit rate is equal to the external clock frequency (the speed of the chip) divided by the period for each bit transmission. This is shown in the period section of the table.

As you can see it has 12Pclk and 4Pclk as the periods available.

12Pclk is for compatiability issues with the 8051 architecture. It gives 2.5Mbps with the 30MHz of the crystal frequency.

4Pclk gives the fastest speed 7.5Mbps.

Some people got tclk/2 for the serial communications. This is actually the clock divider for slowing down the serial communications.

When it says 8, 9, 10, or 11 bits it's talking about the communication protocol not the bit rate.

Having the words "SPI" or "synchronous" in your answer and indicating it's supported. (0.5 mark)

Getting the answer 7.5Mbps.
(0.5 mark)
____________________________________________

Well anyway I need to goes back to looking for a datasheet on the chip that is actually more detailed than the one that was originally provided.

For some reason the other students doing other chips found additional more detailed datasheets when doing their assignments. However, the ones doing this chip didn't. Sick of saying I know this occurs to them (from reading other 8051 datasheets), and want to actually give them a proper reference.

I wonder which of the students I'm marking it was that wrote that....

The assignment was meant to be a learning exercise to teach them how to read datasheets, and find information.

Here's the marking comments just about all of them are getting.
____________________________________________
The chip does support synchronous serial communication. The table for the Serial Port 0 Control (SCON0) on page 38 of the MSC datasheet shows that mode 0 allows for synchronous communication on the serial port.

The maximum bit rate is equal to the external clock frequency (the speed of the chip) divided by the period for each bit transmission. This is shown in the period section of the table.

As you can see it has 12Pclk and 4Pclk as the periods available.

12Pclk is for compatiability issues with the 8051 architecture. It gives 2.5Mbps with the 30MHz of the crystal frequency.

4Pclk gives the fastest speed 7.5Mbps.

Some people got tclk/2 for the serial communications. This is actually the clock divider for slowing down the serial communications.

When it says 8, 9, 10, or 11 bits it's talking about the communication protocol not the bit rate.

Having the words "SPI" or "synchronous" in your answer and indicating it's supported. (0.5 mark)

Getting the answer 7.5Mbps.
(0.5 mark)
____________________________________________

Well anyway I need to goes back to looking for a datasheet on the chip that is actually more detailed than the one that was originally provided.

For some reason the other students doing other chips found additional more detailed datasheets when doing their assignments. However, the ones doing this chip didn't. Sick of saying I know this occurs to them (from reading other 8051 datasheets), and want to actually give them a proper reference.

"I wonder which of the students I'm marking it was that wrote that...."

Another student well and truly rumbled:

http://www.8052.com/forum/read.phtml?id=8648

I trust that they lose extra marks for being so naive as to assume that lecturers can't use the internet?!

I can never shake the nagging feeling that these guys are the ones working on the control system for my antilock brakes.