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C932 High Sleep Power Drain???

Using a C932. In sleep mode we ought to be at about 2uA - instead we sit at 25uA. This is with the part with I/O lines in the air, external xtal, VCC and ground. We have done everything in the book, but still this high power drain, making the chip useless in a battery application.

Anybody out there see anything close to book power in sleep mode?

Thanks!

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  • Here was the problem and solution:

    "Without any programming changes the WDT oscillator will continue to run during power down, consuming approx. 50 mA. To prevent this from happening, the user software has to switch the clock source for the WDT to PCLK. This can be done by clearing the bit WDCLK in register WDTCON followed by a feed sequence. With PCLK selected as source for the WDT, the WDT oscillator will go into power down together with the rest of the chip."

    http://www.lpc900.com/pdf/single-battery.pdf

    Note we had the WD off, but without this change it was still doing something.

    THANK YOU LPC900.com !!!!!!