I am looking at a development project that will require code banking. The target processor will most likely be the Triscend E5 family. I am wondering what effect code banking has on overall efficiency. I have searched the Keil web-site, but there is surprisingly little information available. The code will naturally break up into tasks that, in general, only require to make calls and references to code memory within the same code bank. Although I use the word task, the code will almost certainly be single threaded apart from some ISRs. Is it possible to advantageously place such tasks of code into one bank? Can common code such as library functions and ISRs be placed in common memory? The objective here is to minimise the frequency of bank switches. Does anybody have any advice based on practical experience?
on or off the subject? Graham, You are making a new development with the E5. Do you have any knowledge of the future of this chip after the takeover?. Everything I have read is that ARM is all excited about the E7 - no mention of the E5 whatsoever. Erik
Eric: It is a software development supported on existing hardware so I am stuck on E5. Word from our distributor is that there will be no problem getting E5s in the future.