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Cygnal C8051F020 Simulated Timing

While simulating the Cygnal C8051F020 microcontroller, I found the 'states count' is not accurate. Branching operations have a different cycle count depending on if the branch is taken and this is not correctly simulated.

Is this an error? If so, will it be fixed?

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  • For example, the following loop results in two different timings for the processing of the DJNZ operation of the Cygnal processors:

    MOV R1, #2
    LOOP: NOP
    DJNZ R1, LOOP

    When R1 != 0, the timing is 3 cycles for the DJNZ operation, whereas when R1 = 0 the timing for the DJNZ is 2 cycles. This is a feature of the micros from Cygnal where execution time is optimized. You can verify this via thier datasheets. I see that the DCYG.DLL library provided with C51 has exported routines that deal with state timing and such. I thought maybe the DLL incorrectly processed the Cygnal operations.

    I'm trying to use the simulator for accurate timing measurements.