We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
The question is about far memory type. I use 8951RD2. I define: LX51 and AX51, use on-chip XRAM, support far memory type. The on-chip XRAM of RD2 is 1.7Kb. In listing far memory defined as HDATA. I define variable of type far 440 bytes, and it passes compiling. The listing: MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 3444 ---- CONSTANT SIZE = 50 ---- XDATA SIZE = ---- ---- PDATA SIZE = ---- ---- DATA SIZE = 16 24 IDATA SIZE = 28 5 BIT SIZE = 4 2 EDATA SIZE = ---- ---- HDATA SIZE = 440 ---- XDATA CONST SIZE = ---- ---- FAR CONST SIZE = ---- ---- END OF MODULE INFORMATION. But, if I define far memory 4000 bytes, it also passes compiling. HDATA SIZE = 4000 ---- (remember? 1.7Kb maximum) Why? Where are these variables fisically allocated?
Where are these variables fisically allocated? Elsewhere. :-) Seriously: they're wherever you configured the far data system of C51 to put them. Your chip (8951RD2 isn't quite a usable name --- but it seems you're talking about the AT89C51RD2) has an external memory bus, too, not only on-chip XRAM, right? So there's nothing stopping your board from providing 64K of external XRAM to the cpu, is there? I don't think the "use internal XRAM" means to use only that.
"I don't think the 'use internal XRAM' means to use only that." I don't know if the same applies for all variants but, with the Triscend E5, checking the 'use internal XRAM' box is merely a shortcut to tell the Linker that the size of available XDATA space is the size of the internal XRAM as listed in the Device Database. There is no difference between checking the 'use internal XRAM' box, and manually typing the corresponding values into the XDATA size boxes. The only purpose of this setting is to allow the Linker to warn you when you've used too much XDATA! In particular, note that these settings do not do anything to setup the chip (SFRs, etc) to use its on-chip XRAM.