I/O Port simulation

Is your P0 configured as an outport port? Are you using the external memory space, in which case P0 is part of the data/address bus?

Thans a lot.

I known the bug of uVision simulator.

When I set the value of P0(SFR). It's value will not synchronize with PORT0(VTREG).

But in real world. The value of P0 is always equas to corresponding Pins.

It's a serious bug.

I hope keil will correct in next version.

I don't think you really found a bug.

First, your assertion that in an actual 8051, the state of the physical port pins and the internal register (P0) simply isn't true.

Second, you can have those bits in P0 that are supposed to reflect pin states, i.e. the corresponding bits in the VREG PORT0, react in real-time. Just toggle View->Periodic Window Update.

The problem you are having is caused NOT by a bug but by the accurate simulation of P0.

If you take a look at the 8051 data sheet, you'll find that P0 requires external pull-up resistors if you intend on using it as an I/O port. Port 1, 2, and 3 do not (they have internal pull-ups).

The uVision2 simulator accurately simulates this.

You can add simulation for external pull-ups by writing a short signal function. For example:

signal void pullup_p0 (void) {
while (1) {
  wwatch (D:0x80);
  PORT0 = P0;
  }
}

pullup_p0 ();

Jon Ward is right.

Your explanation is a perfect answer of my question.

Thank you very much.

Actually, to be even MORE precise, the signal function should appear as follows:

define char P0_copy

P0_copy = P0;

signal void pullup_p0 (void) {
while (1) {
  wwatch (D:0x80);
  PORT0 = (PORT0 | ~P0_copy) & P0;
  P0_copy = P0;
  }
}

pullup_p0 ();