Can an interrupt of higher natural priority interrupt one of lower priority? For the time being my question is limited to the case where none of the interrupts' priorities are promoted in the IP. I'm using the Dallas DS80C320 part. I have tried a variety of hardware experiments which suggest that a higher natural priority interrupt CANNOT interrupt one of lower priority but these experiments have not been conclusive (i.e. I have not seen a higher priority event interrupt a lower priority event on my emulator). From what I've observed it seems that the priority scheme only affects which interrupt runs first if both occur during the same machine cycle. In that case both run sequentially, higher priority first, returning to execute one line of code, then second priority. However I'm not entirely confident that I've covered all the possible use cases. I have not been able to get a straight answer from the part vendor (Dallas). They have suggested that the LJMP from the interrupt event to the ISR vector can itself be interrupted. This seems wrong. The reason for this question is that I've ported the uC/OS multi-tasking operating system to my part and I've experienced some intermittent problems when external interrupts are introduced into the system. The OS relies on a CPU context dump to XDATA being performed upon entry into an ISR and this sequence cannot be interrupted, hence my question. I'd appreciate input from anyone with more experience on this part or with '51 interrupts in general. Thanks in advance, Chip Burns
Hi, Correct, line 3(CLR EA) is as you say not needed, although I can't see any harm in leaving it in unless you perhaps intend using higher priorities can interrupt later? Mark.
This is very well described in the '51 'bible'. At http://www.8052.com/links.phtml under "intersting sites" you will find links to chapters 1, 2 and 3 of the '51 "bible". Erik