When enabling the internal xdata memory (XRAMEN EQ 1 in START_AD.A51), writing to the flash/EE data memory fails with error code 15 in ECON in the code below. If XRAMEN is set to 0, xdata does not work, but writing to the flash/EE data memory works. What do I have to do so I can use the internal xdata memory and write to the flash/EE data memory?
int SpWrite(int adress, char b1, char b2, char b3, char b4) { int high = adresse >> 8; int low = adresse & 0xFF; int ret; EADRH = high; EADRL = low; EDATA1 = b1; EDATA2 = b2; EDATA3 = b3; EDATA4 = b4; ECON=5; // Erase ECON=2; // write ECON=4; // verify ret = ECON; return ret; }
The startup code generated by CA51 contains misleading comment that ends up setting SFR CFG831 to 0x1 instead of 0x11. Bit 0 of SFR CFG831 (0xAF) controls the internal xdata memory. To enable xdata, set this bit to 1. Default value is 0x10, so with xdata enabled, the value should be 0x11. XRAMEN in START_UP.A51 needs to be set to 0x11 and not 0x1. START_UP.A51 generated by CA51 contains this code:
XRAMEN EQU 1; 0 = disable on-chip XDATA RAM and access off-chip XDATA space ; ; 1 = enable on-chip XDATA RAM - this should read 11 instead of 1!
This is total absolute gobbelygook. If you want to discuss features unique to a certain derivative STATE WHAT DERIVATIVE you are discussing Erik
"This is total absolute gobbelygook. If you want to discuss features unique to a certain derivative STATE WHAT DERIVATIVE you are discussing" How rude can you get? Try reading the post before yelling at people. Stefan
Hmmmm, Bit 4 of CFG831 has nothing to do with enabling on-chip XDATA in the Analog Devices ADuC831. The Analog Devices datasheet specifies that Bit 4 is EPM2 which is one of the 3 configuration bits for FLASH/EE Controller and PWM Clock Frequency. The Power-On-Reset value for this bit is 1. However, EPM0, EPM1, and EPM2 must be set so that OSC Frequency / 2^(5+EPM2..EPM0) = 32kHz +- 50%. I've sent this to engineering. They will include these new bits in the startup file. Jon