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Hello Forum, is there anybody who has implemented the Inter-IC-Sound protocol with a 80C167? It's a simple synchronous serial protocol, the C167's SSC seems to be o. k. for that, but with the exception of the word strobe signal: The Clock is continously running. To recognize the first bit of a word (and synchronize the SSC) it must be synchronized with the word strobe signal. My first (only mental) approach is to clear SSCBC on a transition of word strobe signal. This could be done via Pec, but eventually this isn't fast enough. In addition, the manual claims: "Do not write to SSCBC!!!" Any ideas are welcome! Thanks - Peter
Actually I've never heard about that protocol before, but my idea is to catch the first bit of the word by software and then try and tune the SSC to receive the remaining 15 (or whatever) bits automatically. - Mike
Hello, take a look at
http://www.semiconductors.philips.com/acrobat/various/I2SBUS.pdf
That looks like a challenge! If you can't skip the very first frame, I think it's impossible without some external clock-gating logic. The microcontroller just isn't fast enough. If you don't mind skipping a few leading frames, you can try and synchronize by software. Generate an interrupt on transition on the word strobe line using fast external interrupt (which should be 100ns accurate.) Then generate a delay in software (you can do that with 50ns accuracy with branch instructions.) Then start the SSC. To provide fixed interrupt response time, the microcontrolle must be in a well-defined state (idle, for instance.) After experimenting with different delay times hopefully you'll be able to start the SSC at the right time. Of course, it is assumed that the bitrate is constant. And still it's not guaranteed to work. There are some other ideas, but they all involve external clock-gating logic. Best luck! - Mike
Hello, thanks for your ideas. I think, it's better to do it with clock gating. My idea: I'll use a flip flop, asynchronously resetable by C167, setable by Word Strobe edge, to gate the clock pulses. To start this way is no problem, because a few missing frames aren't a problem. But, as you might guess, I want to receive audio data, therefore this should run, once started, for, lets say, some hours. If just one clock pulse was missing or one accidently inserted by some sort of interference, all the following audio words will be distorted to be noisy sounding. I've got by the moment only the idea to interrupt C167 by word strobe and read SSCBC and compare the read values. If the C167 is in a known state _most_ of the time, the value should be the same _most_ of the time. Excessive occurs of a wrong value should lead to a new synchronising. The noisy sound should be limited this way to about a few tenth of milliseconds. What are you thinking about that? Any ideas are welcome. Thanks - Peter
You can use the transmitter of the SSC to continuously transmit some synchronization word (say, 0x8000 or something like that) which can be used by external logic to derive "loss of synchronization" signal. I'm pretty sure that you can transmit and recieve simultaniously with the SSC because I used this feature to send ACKNOWLEDGE bit when simulating I2C with the SSC. - Mike
Hello, that sounds just fine. I'll do some thoughts about that. THANKS. Maybe sending $FF00 and do an exor externally, which output will be synchronized. BTW: Did you implement an I²C master or slave? Did you implement I²C with SSC including Clock Longing? With "clock longing" I mean the possibility for slaves (and masters) to delay transfers by pulling clock low? Greeting - Peter