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How to disable interrupts realtime safely

Peter Muthesius

Hello Forum,

I wanna disable interrupts on my 80C167. As far as I understood the User Manual, writes to the PSW (containing the IEN bit and the Interrupt-Level) will take place about two cycles later, which leads to the following effect: If during this very two cycles an Interrupt Request occurs, this interrupt will be accepted and executed, while the PSW-changes took place. This means, during the execution of the interrupt service routine, all other interrupts are disabled, even the higher prioritized, which leads to problems, in particular if it takes a long time to execute. This is what I mean by "realtime unsafe".

If I use

#pragma DISABLE
the compiler genrates code which change the PSW. It inserts two NOPs, protecting the following code from being interrupted, but not preventing the system to be realtime unsafe.

As far as I know, to disable interrupts realtime safely, I have to either use the xxIC-Register, what is quite boring if I got to disable a lot of interrupts. Or, I have to protect the PSW-changing code itself by an ATOMIC.
Am I right in that point? How can I disable interrupts realtime safely in a C-Programmer-friendly way?

Thanks for all opinions and hints - Peter

Parents
  • 0

    I never thought of the possibility that an interrupt service routine can be executed with the IEN flag cleared. The manual clearly says it's possible. Section 'Interrupt and Trap Functions -> Interrupt System Structure -> Interrupt Control Registers -> Interrupt Enable Bit IEN':
    'When IEN is cleared, no new interrupt requests are accepted by the CPU. Requests that already have entered the pipeline at that time will process, however.'
    It seems that for realtime safety one has to use ATOMIC with PSW-modifying code (or modify xxIC registers, which indeed can be boring).
    Thanks for the warning!
    Mike.

Reply
  • 0

    I never thought of the possibility that an interrupt service routine can be executed with the IEN flag cleared. The manual clearly says it's possible. Section 'Interrupt and Trap Functions -> Interrupt System Structure -> Interrupt Control Registers -> Interrupt Enable Bit IEN':
    'When IEN is cleared, no new interrupt requests are accepted by the CPU. Requests that already have entered the pipeline at that time will process, however.'
    It seems that for realtime safety one has to use ATOMIC with PSW-modifying code (or modify xxIC registers, which indeed can be boring).
    Thanks for the warning!
    Mike.

Children
  • 0 in reply to Mik Kleshov

    Hello Mike,

    the statement you referred to says only that you have to add NOPs or other interruptileable stuff after changing PSW and before you are "IRQ-Safe".

    We have to keep two different things apard:

    - Machine commands after PSW-change take place before being "IRQ-Safe".
    - Interrupt Accepatance in this gap leads to unwanted higher-level-interrupt-blocking.

    The Keil #pragma DISABLE code keeps in mind the first point (by adding two NOPs), but in my opinion doesn't handle the second point. But there is another thing that maybe could happen. Please see my answer to my answer to Scott's posting.

    Thanks - Peter