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RAM code solution and troubles

gouezel yann

Mapping externe:
Code:EPROM 00000--01FFF
Code:RAM 12000--1FFFF
Data:RAM 02000--0F6FF

External logic manage the A16 line of RAM chip:
- A16=1 on falling edge of ALE
- A16=0 when RD or WR = 0

My code is stored in 2 I2C eeprom. The Boot code download it in upper RAM (A16 force to 1), then goes in automatic mode described before.

Every things seams ok (sumckeck test works...) BUT I have a very strange behaviour: one program (A prog) works and another one (B prog) doesn't work. The only difference between them is local variable of a function. The A prog has int myVar; and the B has int idata myVar;

My target is a C505CA from infineon and I use the small model. My internal ramsize is 256. I have check in detail the both M51 file the overlay of memory. It seams to be ok.

To be sure that A prog works correctly I need to check two things:
1) my hardware solution
2) why the affectation of idata in local variable generates troubles

Parents
  • 0 in reply to Andrew Neil

    My applicative program is compiled with the NOIV derective. The vector process is written in assembler.

    Is there any particular reason why you do this? Why not just let the Compiler take care of it? -> 1st to be not dependant of interrupt address in my applicative program (applicative be downloaded by the CAN bus), 2nd to be able may be to use interrupt one day in boot program. With this solution I can use the same fix cod for interrupt in EPROM for my evolutive downloaded applicative code.


    ORG 002Bh ; vector 5
    PUSH it5addr+1
    PUSH it5addr+0
    RET
    I hope you've remembered to use a RETI (not RET) at the end of your Service Routine(s)... -> interrupt routine is written in C with the keyword interrupt. I checked the assembler, and the RTI is used.

    itNaddr is a word in data memory in a fixed memory address. Have you taken care to ensure that the Linker is not putting anything else in those locations? Note that my code use bank register0, and each interrupt use other bank resiter 1, 2, and 3. Don't forget that the Register Banks occupy the bottom 32 bytes of Data memory - are your itNaddr words clear of these?
    -> itNaddr is fixed from address 30H. In M51 linker generated file, I can check the ABSOLUTE segment from address 30H

Reply
  • 0 in reply to Andrew Neil

    My applicative program is compiled with the NOIV derective. The vector process is written in assembler.

    Is there any particular reason why you do this? Why not just let the Compiler take care of it? -> 1st to be not dependant of interrupt address in my applicative program (applicative be downloaded by the CAN bus), 2nd to be able may be to use interrupt one day in boot program. With this solution I can use the same fix cod for interrupt in EPROM for my evolutive downloaded applicative code.


    ORG 002Bh ; vector 5
    PUSH it5addr+1
    PUSH it5addr+0
    RET
    I hope you've remembered to use a RETI (not RET) at the end of your Service Routine(s)... -> interrupt routine is written in C with the keyword interrupt. I checked the assembler, and the RTI is used.

    itNaddr is a word in data memory in a fixed memory address. Have you taken care to ensure that the Linker is not putting anything else in those locations? Note that my code use bank register0, and each interrupt use other bank resiter 1, 2, and 3. Don't forget that the Register Banks occupy the bottom 32 bytes of Data memory - are your itNaddr words clear of these?
    -> itNaddr is fixed from address 30H. In M51 linker generated file, I can check the ABSOLUTE segment from address 30H

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