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We assumed that this verry good compiler could recognice "for" statements moving bytes from one buffer to another. This seams not to be right. From the manual I can se that the dual dp only works with a limited number of lib functions (strcpy, memcpy...) Do anyone have experience in using dual dp on dallas 320 and do we have to set up any directives for the compiler to use the dual dp all over the program. Henning
The benchmarks show a significant difference between "small" (on the order of 1-10) and "large" (on the order of hundreds & thousands). How much of this is due to the overhead of the Generic Pointers? Do you have corresponding benchmarks using memory-specific pointers; eg,
void xdata *memcpy_xdata_xdata( void xdata *dst, void xdata *src, unsinged char end, unsigned int len )
The benchmarks show a significant difference between "small" (on the order of 1-10) and "large" (on the order of hundreds & thousands). How much of this is due to the overhead of the Generic Pointers? Do you have corresponding benchmarks using memory-specific pointers; eg, I guess we could have written a really crappy memcpy that doesn't know about the memory areas, but we didn't. :-) That's why you like the Keil compiler so much! The memcpy routine figures out which memory area you are reading and which area you are writing and invokes a specific routine to copy the data. Therefore, the routine you suggest would be faster only by 4 or 5 instructions (the ones that figure out the source and destination memory areas). There only need to be the following:
CODE -> XDATA CODE -> IDATA XDATA -> XDATA XDATA -> IDATA IDATA -> XDATA IDATA -> IDATA
loop: movx a,@dptr ; 2 cycles inc dptr ; 2 cycles xch a,r0 ; 1 cycle xch a,dpl ; 1 cycle xch a,r0 ; 1 cycle xch a,r4 ; 1 cycle xch a,dph ; 1 cycle xch a,r4 ; 1 cycle movx @dptr,a ; 2 cycles inc dptr ; 2 cycles xch a,r0 ; 1 cycle xch a,dpl ; 1 cycle xch a,r0 ; 1 cycle xch a,r4 ; 1 cycle xch a,dph ; 1 cycle xch a,r4 ; 1 cycle djnz r7,loop ; 2 cycles djnz r6,loop ; 2 cycles
loop: movx a,@dptr ; 2 cycles inc dptr ; 2 cycles inc dps ; 1 cycle movx @dptr,a ; 2 cycles inc dptr ; 2 cycle inc dps ; 1 cycle djnz r7,loop ; 2 cycles djnz r6,loop ; 2 cycles
Does C51 ever use more than 2 DPTRs, if the chip supports it?
Yes, The Infineon C517 type devices are the only ones that I know of that have more than 2 data pointers. For these devices, C51 uses one PAIR of data pointers for each register bank. Jon