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If I understand correctly, the Intel 151 trimmed the instruction cycle from 12 clocks to 4 clocks. The small app note pamphlet I have on it illustrates this in different external timing diagrams. My question is, however, are all internal instruction cycles trimmed to 4 clocks per cycle as well? This is a question of calculating code execution time. With a normal 12-clock/cycle 8051, I count up the instruction cycles then mutiply by the XTAL / 12. Is it correct to assume that for the 151 I should do the same but multiply by XTAL / 4 ??? Your feedback is appreciated.
Jon, Thx for the reply. I realize I should have said 4 / XTAL. Sorry. Just the same, my question is in regard to clocks/intruction. Example (non-pagemode): mov a, #23 If I read the timeing diagrams correctly, this two-byte instruction will take 8 clocks, where this clr a will require only 4. In a standard 51, both of these require 12 clocks ... despite the fact that the first is a 2-byte instruction and the second is 1-byte. It seems the 151 instruction cycle time is now more dependant on the number of bytes per instruction than the original 51. I have an instruction chart for a standard 51 and by each there is a bytes/cycles indicator. I wish I had the same chart for the 151.
Take a look at the following data sheet. http://www.keil.com/DD/docs/datashts/intel/8xc151sx_ds.pdf The last chapter lists the number of execution states for each instruction. The mov a, #23 instruction takes only 1 state, not 2. Jon
Wow! Thanks Jon. This is exactly what I've been looking for. BTW, don't you work for Keil? I think I've spoken with you in the past.
Wow! Thanks Jon. This is exactly what I've been looking for. BTW, don't you work for Keil? I think I've spoken with you in the past. Yep. I work for Keil. Jon