Hello, I am looking for a sophisticated RAM-Check-algorithm, that does not only detect problems with one cell like a simple write and read back. It should also be able to detect short ciruits and breaks of address-lines and maybe timing problems on the address-bus. Thanks!
Back in the old days when DRAM was a new technology, MOSTEK published a test that used an XOR of the address being written, and a counter. You set the counter to 0, and then XOR lsb and msb of address and the counter, then wrote the result to the address. You incremented the address using the same count value and continued until all of ram was filled. You then read it back, generating the compare value with the same algorithm. When this pass was done, you incremented the counter and did the sequence again. This is repeated until the counter cycled to FF. This method generates a unique, non-repeating pattern in memory, allowing detection of stuck bits, address errors, etc. Most people don't use this today, as both SRAM and DRAM are much more reliable. However, this test does give a thorough test of the device. It will take a long time to execute though. Sorry I can't give you the exact algorithm, but I don't have the data book that contained it anymore. It was in the old MOSTEK DRAM data book, circa 1979-1980. Another good test is an n-squared test, in which each location is accessed from every other location. This gives a thorough test of the device, including its internal hardware for driving address lines.