Hello, I am looking for a sophisticated RAM-Check-algorithm, that does not only detect problems with one cell like a simple write and read back. It should also be able to detect short ciruits and breaks of address-lines and maybe timing problems on the address-bus. Thanks!
SRAM is a lot easier to test than DRAM. Assuming that you are using SRAM, do the following tests: 1) Checkerboard. Write 0x55 to even locations, 0xAA to odd locations. 2) Inverse checkerboard. Write 0xAA to even locations, 0x55 to odd locations. 3) Address pattern. To each location write: 0xC3 xor (address[23:16]) xor (address [15:8]) xor (address[7:0]) The 0xC3 constant is an arbitrary initial value. In all tests verify after all locations have been written. The checkerboard tests handle all stuck bit cases and many adjacent cell dependency cases. The address pattern test handles all address line open and short cases. If you have 16-bit wide RAM, then modify the algorithms accordingly. You should make sure that timing is correct by design. The only way to test for timing problems is to run continuous RAM tests while varying supply voltage and ambient temperature.
Beware of verification by just writing to a location and then immediately reading it back: this sort of test can pass with the RAM chips not fitted! (there can be enough capacitance to hold the pattern long enough for the read to "verify" correctly!)
That's right. Maybe I wasn't clear, but I did say verify after all locations have been written. In other words, write the entire RAM, and then verify the entire RAM.
Greg, Yes, you did! There was another reply in the thread which didn't seem so clear, but my reply seems to have been attached to your post. Sorry. Maybe this board just gets a little confused in its threading with different timezones (I'm on GMT in the UK). Rgds, Andy.
heiio, my name is ashish and i what to know the price of every types of ram check. thank u