I have connected an FPGA to PORTB (data), RDY4 (SLWR) and RDY0 (ASEL). I programmed ABSETUP.5 (async mode), IFCONFIG.0, and IFCONFIG.1 to ones. ABPOLAR is all zeros, my control signals active low. Still no data in FIFO A. The SLWR and ASEL work fine and correct data can be seen in PORTB pins if I set IFCONFIG bits to zero and read PINSB. Are there other control bits to be set? Thanks, Harri