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Iam designing the DDR IP with AXI4 SLAVE INTERFACE 

1. If DDR MEMORY IS HAVING BURST LEN OF 16 , THEN HOW CAN WE DECIDE ON THE axi4 slave burst length support .

2.How many multiple outstanding transaction should the AXI4 Slave need to support on what parameter it is decided  while building the IP .

3.How is the address width of AXI4 SLAVE INTERFACE CALCULATED while building the DDR IP. 

4. In Narrow Burst support , Write strobe is used in write operation to indicate which bytes is valid but how we can identify during read operation as we dont have any read strobe ?