The license of glibc requires referenced code to be open-source, but amath is closed-source. Are there any license issues with using it?, exsample expf, While the register names differ, the computational logic, conditions, and the arm_math_exp_data remain entirely identical.
arm_math_exp_data
__expf_finite@GLIBC_2.17: fmov w0, s0 fcvt d2, s0 ubfx x1, x0, #20, #11 cmp w1, #0x42a b.hi 3fd78 <__expf_finite@GLIBC_2.17+0x68> // b.pmore adrp x0, 78000 <f64xsubf128@@GLIBC_2.28+0x29250> add x0, x0, #0x830 fmov d1, #1.000000000000000000e+00 ldp d0, d4, [x0, #296] ldr d3, [x0, #312] fmul d2, d2, d0 ldr d0, [x0, #320] frinta d5, d2 fcvtas x1, d2 fsub d2, d2, d5 and x2, x1, #0x1f fmadd d3, d4, d2, d3 fmadd d0, d0, d2, d1 fmul d2, d2, d2 ldr x0, [x0, x2, lsl #3] add x1, x0, x1, lsl #47 fmov d1, x1 fmadd d0, d3, d2, d0 fmul d0, d0, d1 fcvt s0, d0 ret cmn w0, #0x800, lsl #12 b.eq 3fde0 <__expf_finite@GLIBC_2.17+0xd0> // b.none cmp w1, #0x7f7 b.hi 3fdd8 <__expf_finite@GLIBC_2.17+0xc8> // b.pmore mov w0, #0x7217 // #29207 movk w0, #0x42b1, lsl #16 fmov s1, w0 fcmpe s0, s1 b.gt 3fdc8 <__expf_finite@GLIBC_2.17+0xb8> mov w0, #0xf1b4 // #61876 movk w0, #0xc2cf, lsl #16 fmov s1, w0 fcmpe s0, s1 b.mi 3fde8 <__expf_finite@GLIBC_2.17+0xd8> // b.first mov w0, #0x8ecf // #36559 movk w0, #0xc2ce, lsl #16 fmov s1, w0 fcmpe s0, s1 b.mi 3fdd0 <__expf_finite@GLIBC_2.17+0xc0> // b.first b 3fd24 <__expf_finite@GLIBC_2.17+0x14> mov w0, #0x0 // #0 b 4cc00 <__exp2f_finite@GLIBC_2.17+0x1e90> mov w0, #0x0 // #0 b 4cbf0 <__exp2f_finite@GLIBC_2.17+0x1e80> fadd s0, s0, s0 ret movi v0.2s, #0x0 ret mov w0, #0x0 // #0 b 4cbe0 <__exp2f_finite@GLIBC_2.17+0x1e70>
armpl_exp_f32: fmov w0, s0 fcvt d31, s0 ubfx x1, x0, #20, #11 cmp w1, #0x42a b.hi 159e4 <armpl_exp_f32+0x64> // b.pmore adrp x0, 5f000 <arm_math_exp_data+0x570> add x0, x0, #0x7b0 fmov d0, #1.000000000000000000e+00 ldp d30, d28, [x0, #288] fmul d31, d31, d30 ldp d30, d29, [x0, #304] frinta d27, d31 fcvtas x1, d31 fsub d31, d31, d27 and w2, w1, #0x1f fmadd d30, d28, d31, d30 fmadd d0, d29, d31, d0 fmul d31, d31, d31 ldr x0, [x0, w2, sxtw #3] add x1, x0, x1, lsl #47 fmadd d0, d30, d31, d0 fmov d31, x1 fmul d0, d0, d31 fcvt s0, d0 ret cmn w0, #0x800, lsl #12 b.eq 15a4c <armpl_exp_f32+0xcc> // b.none cmp w1, #0x7f7 b.hi 15a44 <armpl_exp_f32+0xc4> // b.pmore mov w0, #0x7217 // #29207 movk w0, #0x42b1, lsl #16 fmov s30, w0 fcmpe s0, s30 b.gt 15a34 <armpl_exp_f32+0xb4> mov w0, #0xf1b4 // #61876 movk w0, #0xc2cf, lsl #16 fmov s30, w0 fcmpe s0, s30 b.mi 15a54 <armpl_exp_f32+0xd4> // b.first mov w0, #0x8ecf // #36559 movk w0, #0xc2ce, lsl #16 fmov s30, w0 fcmpe s0, s30 b.mi 15a3c <armpl_exp_f32+0xbc> // b.first b 15994 <armpl_exp_f32+0x14> mov w0, #0x0 // #0 b 54a00 <arm_math_oflowf> mov w0, #0x0 // #0 b 549e8 <arm_math_may_uflowf> fadd s0, s0, s0 ret movi v0.2s, #0x0 ret mov w0, #0x0 // #0 b 549e0 <arm_math_uflowf> nop