Hi sir,
T1=NON-SEQ
T2=BUSY
T3=SEQ
T4=SEQ
T5= SEQ
This is for WRITE operation:
i am using a BUSY state for T2. Then my WAIT state for till T3. I have read from the forum if WAIT state u are using a BUSY transfer, you can change next clock on the valid transfer.
If i change the HTRANS to the valid transfer my T1 data will be maintained for till T3 clock. Then what about the BUSY transfer.
This same as applicable for READ operation.And this is only for WAIT STATE.
Regards
Rajaraman R
Just so that I fully understand what you are describing, could you draw a diagram, or explain what you are driving HREADY to in each clock cycle ?
It looks like you might be describing HREADY driven low in cycle T2 coinciding with the BUSY transfer address phase, in which case the following would apply.
You can change HTRANS at the start of T3 to SEQ. During the T2 and T3 cycles, the HWDATA bus will have the T1 transfer write data. For a read transfer the HRDATA value is undefined for cycle T2 because the slave is signalling a wait state, but would be the requested read data in cycle T3.
In this scenario the BUSY cycle is never sampled by the system (because it was never seen on HTRANS at the same time as HREADY being high), so essentially the BUSY transfer never happened
Thank You Collin for your answer.
I still have a doubt that at T2 i am sending busy from master to slave in my HTARNS then how come my slave can send me HREADY=LOW at same instance of time i.e T2.
Slave might get this acknowledgement at next rising edge of clock which is T3,so i guess at T3 HREADY should go low,But at T2 its getting low.
So,is there any connection between HTRANS and HREADY.
Waiting for your response.
Thanks in advance.
MUKUL.P