Hello,
I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.
1) I would like to know how read and write address requests issued to slave are associated with read or write data. Is it based on AWID/ARID?
2) Is there any max. latency specified by AMBA specification with respect to read request and corresponding read response?
3) Can AMBA have different (sort of asymmetrical) bus width for read & write data widths?
4) in AMBA spec., there is a mention about 3 different topologies (shared address and data buses, shared address and multiple data buses & multiple address and data buses).
This is confusing to me. Masters and slaves connect to interconnect matrix independently. So, I don't understand what is meant by shared address and data.
TIA, Sbr
Dear Yashuhiko San,
Thanks a lot. The figures on the interconnect schemes helped me a lot.