AXI-4 questions

Hi Sbr,

1) I would like to know how read and write address requests issued to slave are associated with read or write data. Is it based on AWID/ARID?

AR bus and AW bus are independent.
For each address channel, the addresses are issued in order (especially AXI4 does not support write interleaving, it would be so) but the responses would be out of order. The pairing between an address and a response would be performed by AWID/ARID.

2) Is there any max. latency specified by AMBA specification with respect to read request and corresponding read response?

No, there is not such description in the specs.

3) Can AMBA have different (sort of asymmetrical) bus width for read & write data widths?

It probably cannot.
In the AMBA specs, there are no such configuration described and seem not to be prohibited.
However, the AMBA designer can be specified only one DATA_WIDTH for each the read channel and the write channel, and it would be reasonable that such a configuration was not permitted.

4) in AMBA spec., there is a mention about 3 different topologies (shared address and data buses, shared address and multiple data buses & multiple address and data buses). This is confusing to me. Masters and slaves connect to interconnect matrix independently. So, I don't understand what is meant by shared address and data.

'Masters and slaves connect to interconnect matrix independently' would be ordinary but incorrect.

You would say about the multi-layer type interconnect.

The outlook would be the same for each topology, but the internal structures are different according to the topologies. Please look at the Figure 1 to 3 for your reference.

Best regards,

Yasuhiko Koumoto.

Hi Sbr,

1) I would like to know how read and write address requests issued to slave are associated with read or write data. Is it based on AWID/ARID?

AR bus and AW bus are independent.
For each address channel, the addresses are issued in order (especially AXI4 does not support write interleaving, it would be so) but the responses would be out of order. The pairing between an address and a response would be performed by AWID/ARID.

2) Is there any max. latency specified by AMBA specification with respect to read request and corresponding read response?

No, there is not such description in the specs.

3) Can AMBA have different (sort of asymmetrical) bus width for read & write data widths?

It probably cannot.
In the AMBA specs, there are no such configuration described and seem not to be prohibited.
However, the AMBA designer can be specified only one DATA_WIDTH for each the read channel and the write channel, and it would be reasonable that such a configuration was not permitted.

4) in AMBA spec., there is a mention about 3 different topologies (shared address and data buses, shared address and multiple data buses & multiple address and data buses). This is confusing to me. Masters and slaves connect to interconnect matrix independently. So, I don't understand what is meant by shared address and data.

'Masters and slaves connect to interconnect matrix independently' would be ordinary but incorrect.

You would say about the multi-layer type interconnect.

The outlook would be the same for each topology, but the internal structures are different according to the topologies. Please look at the Figure 1 to 3 for your reference.

Best regards,

Yasuhiko Koumoto.