Hi,
When I read the following on Cortex M4F, I don't understand the blue phrase on the uDMA process.
1. Why does it selects the lesser? The arbitration size matters uDMA services here?
2. I remember that DMA burst cannot be interrupt, even by high priority DMA request. Then what use of the
number of items remaining in the transfer here?
Thanks,
//////////////
9.2.4.2 Burst Request
When a burst request is detected, the μDMA controller transfers the number of items that is the
lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration
size should be the same as the number of data items that the peripheral can accommodate when
making a burst request. For example, the UART generates a burst request based on the FIFO trigger
level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer
when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot
be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the
same number of non-burst transfers.
Yes, I mean Tiva-C micro-controller. Here is the link:
http://www.ti.com/lit/ds/symlink/tm4c1299kczad.pdf
It is a surprise to me that uDMA is not an ARM term?
The problem now looks clear to me.
Hello,
It is a surprise to me why you think such a way.The term uDMA will appear only in TI's document.
Have you gotten answer?
Best regards,Yasuhiko Koummoto.