Removal of WID's in AMBA AXI4

Support for "write data interleaving" was added in the AXI3 spec as a way of maximising data bus bandwidth when masters couldn't generate write data in continuous bursts, with the ID allowing a slave to work out which outstanding write data stream the received transfers related to.

However we saw this rarely used as it required more complexity in the masters and slaves involved in generating and decoding the interleaved transfers, and instead designers preferred to buffer up the write data at source and then send it in one continuous burst of write data transfers.

As a result, AXI4 removed support for write data interleaving, which then removed the need for the WID signal (it was only needed to work out which outstanding write transaction the data related to). The primary reason for removing WID was NOT to reduce the interface pin count, it was imply that the WID signal was no longer needed.

So when looking at AXI4 write transactions, the order write data transfers will be seen is defined by the order the write address transfers are seen, with all the data for the first received write address transfer being received before the first data for the second received write address transfer.

"Out of order" transactions are just a particular implementation of "write data interleaving" where later started write transactions can complete before earlier started transactions, so both are no longer supported by AXI4 interfaces.

Support for "write data interleaving" was added in the AXI3 spec as a way of maximising data bus bandwidth when masters couldn't generate write data in continuous bursts, with the ID allowing a slave to work out which outstanding write data stream the received transfers related to.

However we saw this rarely used as it required more complexity in the masters and slaves involved in generating and decoding the interleaved transfers, and instead designers preferred to buffer up the write data at source and then send it in one continuous burst of write data transfers.

As a result, AXI4 removed support for write data interleaving, which then removed the need for the WID signal (it was only needed to work out which outstanding write transaction the data related to). The primary reason for removing WID was NOT to reduce the interface pin count, it was imply that the WID signal was no longer needed.

So when looking at AXI4 write transactions, the order write data transfers will be seen is defined by the order the write address transfers are seen, with all the data for the first received write address transfer being received before the first data for the second received write address transfer.

"Out of order" transactions are just a particular implementation of "write data interleaving" where later started write transactions can complete before earlier started transactions, so both are no longer supported by AXI4 interfaces.