For example, the codes are executed in core0.
codes:
(1) send SGI to core1 ICC_SGI1R_EL1
(2) set(a) = 1
i) Then the core1 will first see the irq or the change of variable a?
ii) If I add ISB between (1) and (2), what happended?
iii) If I add DMB (read and write)between (1) and (2), what happended?
iv) If I add DSB (read and write)between (1) and (2), what happended?
After I tested, it seems that only iv) which add DSB makes core1 see (2) after (1).
I had checked the discription of DSB, I don't think any rules match this.
Any help will be appreciated. Thanks!
I found a NOTICE in <ARM® Generic Interrupt Controller Architecture Specification>
An ISB or other context synchronization operation must precede the DSB to ensure visibility of System register writes.