Dear Community,
In my use case, I start with EL3 mode and switch back to EL2 mode but I am seeing different kind of issues with this switching ,
My code is like
1. u-boot in EL3 (This enable caches, MMU and Stack pointer for EL3) . This stack pointer is in DDR
2- Save Stack pointer in assembly code and set sp_el2 = sp_el3 and call switch routine, by giving its return address .
3- Switch routine , sets up own stack point in internal RAM for EL3 , cache flush , invalidate and at last disable MMU and cache for el3 mode.
4. eret [jump back to EL2 at provided return address, step 2)
4- u-boot continue at EL2
Problem, I am getting , I read DDR at step 2 (location is SP) then read contents are ok
If i read, at the end of step 3, then DDR contents read as 0xdeadbeef.
In case, i remove disable of cache and mmu in step-3, then at the end of step 3 ddr read is ok,
But at step 4, read contents are deadbeef always
Thanks for help
why , if i kept enabled MMU/cache el3 then contents are ok ?
why after eret , CPU is not able to read DDR properly
Thanks
P.S : Some part of memory is read ok always
Hi,
Hard to be sure from the information provided, but...
I suspect your problem relates to the fact that EL3, EL2 & EL1 all have independent "translation regimes". This means each EL needs its own set of translation tables and its own system register initialization (i.e. Each MMU enable & TTBR etc is independent and unique to a specific EL).
Are you sure all your EL2 system registers and translation tables correctly configured before you ERET down to EL2?
If you haven't correctly configured a valid virtual world in EL2, you will get unexpected results when accessing memory.
We don't support the scheme you describe - uboot running at EL3.
Our stack is based on Trusted firmware performing various platform initialization steps before calling a Linux boot loader.
https://community.arm.com/dev-platforms/w/docs/306/bare-metal-development-on-juno may help you.
Regards
MarkN.