I am trying to write a kernel module in C to bring the system in the hypervisor mode. The module is for a router, which is running OpenWrt. The architecture is ARMv7.
When I load my module with insmod I get this error when the module comes to the hvc #0 instruction:
Internal Error: Oops - undefined instruction: 0 [#1] SMP ARM
I am new to ARM and virtualization but so far I have understood that I have to do the following things before calling hvc #0
I have to be in PL1(SVC) mode. Is this given when I load a kernel module instead of a normal C Program?
I have to set the SCR.NS bit to 1.
I have to set the SCR.HCE bit to 1.
I have not understood how to set these bits. I have read that the CPU needs to be in monitor mode for setting these bits, is this true? And how can I do this?
Can someone give me please an example in C or assembly how to prepare the system that I can execute hvc #0.
Hi,
I think your question is a bit outside the scope of this specific Community subgroup (maybe better in one of the more generic areas). But...
Do you know what ARM core you are using?
Arch v7A includes hardware support for Hypervisors - delivered as a set of virtualization extensions. *However* not all v7-A implementations support these extensions.
So the HVC instruction will work with Cortex-A15, which does implement these extensions.
But, If you tried (say) on a Cortex-A9 you'd get an undef in you tried to execute a HVC instruction.
MarkN
Hey, thanks for your answer. I have noticed that the task was not possible with the first router since it does not support the virtualization extensions. Now I have now a new router with cortex A15 (Netgear Nighthawk R9000-100EUS AD7200 Tri-Band Gigabit WLAN Router).
The task is for a scientific project where we want to check if we can place an own hypervisor on a running OS. But before writing this hypervisor we want to check if we can bring the processor in hyp mode. But before we can call the hvc instruction we have to enable the HCE bit and then the NS bit in the Secure Configuration Register. Our actual problem is to set these bits to true. We want to achieve this with inline assembly inside of a C kernel module.
Under http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438c/CIHGIAHG.html I found the information that I can change the SCR with
MCR p15, 0, <Rt>, c1, c1, 0;
But the problem is that the system must be in secure PL1 mode. How it is possible to bring the system in secure PL1 mode, change the bits and then call the hvc instruction, do you have any idea on how to do this?
The next step after we have done this would be to change the HVBAR to control what happens on a hypervisor exception.
Yes - you must be in Secure state to write the SCR. Basically you can't do this from kernel code. It needs to be initialized in firmware (or some code with Secure privilege). The core will reset/boot in Secure state & firmware will generally run at the highest level of privilige