Hi !
on armv7 [1] / aarch32 [2] MMU, when using Long descriptor, when the virtual space described by ttbr0 is small enough (1Gb here), the level 1 translation can be skipped, leaving only two levels of translations.
However I saw nothing of the like in the aarch64 translation description. Does anyone know if it is still possible to reduce the number of translation table used by ttbr0 when using aarch64 ?
A reference in the ARM ARM would be great if it exists.
Best,
V.
[1]: ARMARM v7 , B3.6 Long-descriptor translation table format, Fig B3-12 General view of stage 1 address translation using Long-descriptor format
[2]: ARMARM v8, G4.6.1 Overview of VMSAv8-32 address translation using Long-descriptor translation tables, Fig G4-8