Hey guys,
I need your help because I have to count the number of L2 instruction access, miss and hits. But in the data-sheet I did not find the events that I have to count.
I found it in the ARM V8 data-sheet. Therefore, is it usable on A72 & A53 even if it is not mentioned on their data-sheet.
I work on JUNO r2.
Thanks,
Cortex-A72 and Cortex-A53 are ARMv8 architecture processors. They also support the Performance Monitoring Unit feature. For CA53, please see TRM Section12: infocenter.arm.com/.../DDI0500D_cortex_a53_r0p2_trm.pdf For CA72, please see TRM Chapter 11: infocenter.arm.com/.../cortex_a72_mpcore_trm_100095_0001_02_en.pdf If you have DSTREAM/DS-5 Studio, you can easily check the Juno L1/L2 cache hit/miss rate in a graphics view. Please see user guide Section 6.1 infocenter.arm.com/.../DUI0482F_using_arm_streamline.pdf