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Juno r2 L2 and TLB cache

xpo over 8 years ago

Hey guys,

I need your help because I have to count the number of L2 instruction access, miss and hits. But in the data-sheet I did not find the events that I have to count.

I found it in the ARM V8 data-sheet. Therefore, is it usable on A72 & A53 even if it is not mentioned on their data-sheet.

I work on JUNO r2.

Thanks,

+1 Sudeep Holla over 8 years ago

You need to use the PMUs(Performance Monitoring Unit) to get those L2 cache counters.
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+2 Zhifei Yang over 8 years ago

Cortex-A72 and Cortex-A53 are ARMv8 architecture processors. They also support the Performance Monitoring Unit feature.

For CA53, please see TRM Section12:
infocenter.arm.com/.../DDI0500D_cortex_a53_r0p2_trm.pdf

For CA72, please see TRM Chapter 11:
infocenter.arm.com/.../cortex_a72_mpcore_trm_100095_0001_02_en.pdf

If you have DSTREAM/DS-5 Studio, you can easily check the Juno L1/L2 cache hit/miss rate in a graphics view.
Please see user guide Section 6.1
infocenter.arm.com/.../DUI0482F_using_arm_streamline.pdf
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