NIC -400 supports following
Write acceptance capability of 1-32 transactions
Read acceptance capability of 1-127 transactions
Write issuing capability of 1-32 transactions.
Read issuing capability of 1-127 transactions.
There are 1 master CM7 trying to access RAM/ROM/CSR
Say CM7 is a master which can send 32 write and 7 reads . RAM supports 5 write transaction 4 read and ROM does 5 reads
NIC 400 ASIB will have parameters of 32 write and 7 read
AMIB will be RAM 5 write and 4 read
AMIB will be RAM 0 write and 5 read
Where will these buffer for 32 write and 7 read to be accepted by NIC and outbound buffer of 5 write and 4 read
I believe that these parameters constrain the size of the transactions counters in the NIC-400 and are not used to create any buffers in the NIC-400. The simplest way to define them is to match the capabilities of the connected devices, and all will work correctly.
If the CM7 issued 32 transactions, and all targeted the RAM which can only accept 5 write transactions, AWREADY from the NIC-400 would go low to stall further CM7 transactions after 5 transactions, or possibly a few more depending on what registering and buffering you might define in the NIC-400 interfaces these transactions will pass through.
So you might not be able to use the full issuing or acceptance capabilities of the connected devices, but this will only be a few redundant gates in a NIC-400 counter, so not worth trying to analyse exactly how many transactions could be active on a path through the NIC-400. Set these values based on the external device capabilities.
If you want to configure buffering in the NIC-400, this is a separate configuration, and not controlled by the acceptance and issuing capability parameters.
Note that if you are licensing the NIC-400 IP direct from Arm you can instead use the licensee support portal to get more detailed support, especially where your questions are more technical than just simple queries.