Interrupt signal Bypass in GICv2

Hi all,

ARM® Generic Interrupt Controller - Architecture version 2.0

In GICv2 (2.3.1 Interrupt signal bypass, and GICv2 bypass disable --- Page 2-27)

it is mentioned that CPU interface optionally includes Interrupt signal bypass. i have read that concept but i have few doubts regarding that are confusing me a little bit.

1. When we are using separate module for handling the Interrupts in a system, what is the necessary of interrupt signal bypass.?

2. In what scenario do we have to / does the signalling of the interrupt by the interface is disabled.?

3. what is the interrupt source of this Legacy Interrupt Signal..?

4. In what scenario does the GIC functionality gets disabled and the Legacy Interrupt signal is Signalled..?

5 .Does this Legacy interrupt Signal pass through distributor block.?

6. Does the distributor decide the Group0/Group1 type of that Legacy Interrupt signal..?

7. For Bypass Interrupt Signal how is the processor is going to acknowledge and where it is going to write the End of Interrupt Status..?

8. If legacy Interrupt signal is signalled to the processor and processor is processing that interrupt, in this mean time is there any chance that CPU Interface can be enabled..?

Questions what ever i have asked are as per my understanding, Please correct me if I am wrong.

Thanks in advance,

Rakesh.