Hi, Is it possible when a read transaction is done then slave puts the read data into interface and after that the pready is asserted or is it like when pready and prdata are driven at same time or it is configurable as per the DUT?
PREADY will be asserted by the peripheral when it can drive PRDATA to the required value and meet any setup times for the sampling destination registers.
Whether PRDATA is driven to the required value and only then is PREADY asserted, or they are both driven at the same time, will depend on the peripheral's implementation. As long as PRDATA has a valid value to be sampled on PCLK rising when PREADY is high is all that is important, and it shouldn't be a configurable option in the DUT (unless you are looking at additional registering that will impact on latency to give you guaranteed full PCLK cycle setup times on PRDATA).