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Why does it fail to switch from EL3 to SVC mode ?

mike

(1) I intrrrupt the cpu in UEFI (EL2) by press enter key when the serial outputs the following message.

NOTICE:  Booting Trusted Firmware

NOTICE:  BL1: v1.0(release):14b6608

NOTICE:  BL1: Built : 14:15:51, Sep  1 2014

NOTICE:  BL1: Booting BL2

NOTICE:  BL2: v1.0(release):14b6608

NOTICE:  BL2: Built : 14:15:51, Sep  1 2014

NOTICE:  BL1: Booting BL3-1

NOTICE:  BL3-1: v1.0(release):14b6608

NOTICE:  BL3-1: Built : 14:15:53, Sep  1 2014

UEFI firmware (version v2.1 built at 14:41:56 on Oct 23 2014)

The default boot selection will start in   9 seconds

[1] Linux from NOR Flash

[2] Shell

[3] Boot Manager

(2)I follow the tutorial(Running Bare-Metal code at EL3 on the Juno board) to switch to EL3.

  1. Interrupt the CPU in UEFI (EL2)
  2. Disable the MMU at EL2
  3. Load a stub image containing a single SMC instruction
  4. Single-step the SMC instruction to enter EL3
  5. Disable the MMU at EL3
  6. Reprogram the TZPC to allow Secure world access to Normal world memory regions, such as DDR
  7. //////Load the bare-metal image to be run at EL3

(3)I modified the example project "startup_ARMv8_AArch64_with_AArch32_app" which is located in the example folder of DS5 installation folder.

        It's aimed not to initial the GIC. I download the file "AArch64_startup.axf" at EL3.


(4)I set the PC to the entry point and set a breakpoint to the following "eret" instruction. I step the eret instuction when it runs to the breakpoint.

        PC register changed to the value of "__main", but the CPSR is still EL3h. It failed to switch to SVC mode.

 

   PS:I also run the program in the VE_AEMv8x4 Brae-Metal simulation envirionment and it successed to switch to SVC mode.


drop_primary_to_el1:

    ldr x1, lit___main

    msr ELR_EL3, x1

    mov x1, #(AArch32_Mode_SVC | \

              AARCH64_SPSR_F   | \

              AARCH64_SPSR_I   | \

              AARCH64_SPSR_A)

    msr SPSR_EL3, x1

    eret

      

The problem is why it failed to switch from EL3 to SVC mode.

Parents
  • +1 Arm Employee Badge in reply to mike

    Hello,

    Please can you confirm the value defined for the 'AArch32_Mode_SVC' constant? It should be 0b10011. Note that this is a 5-bit constant, *NOT* a 4-bit constant.

    It's possible that 'AArch32_Mode_SVC' has only been defined as 0b0011, which does correspond to AArch32 Supervisor mode, but that will fail to set bit M[4] of SPSR_EL3, which is required when performing an exception return to AArch32 state.

    Ash.

Reply
  • +1 Arm Employee Badge in reply to mike

    Hello,

    Please can you confirm the value defined for the 'AArch32_Mode_SVC' constant? It should be 0b10011. Note that this is a 5-bit constant, *NOT* a 4-bit constant.

    It's possible that 'AArch32_Mode_SVC' has only been defined as 0b0011, which does correspond to AArch32 Supervisor mode, but that will fail to set bit M[4] of SPSR_EL3, which is required when performing an exception return to AArch32 state.

    Ash.

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