Please note: We are aware of an issue affecting replies on the Arm Community forums, which may not be loading as expected.
We apologize for any inconvenience and appreciate your patience while we investigate and work to resolve the issue.
Thank you for your understanding.
Hello,
In the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, there's a description about vttbr_el2: " Register bits[47:x] hold bits[47:x] of the stage 1 translation table base address" . I am a little confused, as far as I know , the vttbr_el2 register hold the stage 2 page table base address, so what's the meaning of " stage 1 translation table base address"?
Also, I tired to open the 2 stage paging in my system liteblue. I setup the 2 stage page table at physical address(0x20000000), and set the vttbr_el2 to this value.However, I got a Data Abort (code: 000101) which means a level 1 translation fault in stage 2 translation. So what's the correct usage of vttbr_el2?
I am using cortex-a53 and here's the related register value I set:
HCR: 0x80000001
VTCR_EL2: 0x80023558
VTTBR_EL2: 0x20000000