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Data Watch DWT on RPI3 without debuigger

br-dev over 6 years ago

hi,

I am trying to use the Data Watch and Trace natively on RPI3 without debugger to count Cycle but got a core dump. here the code to compile and run on a RPI3. . My objective is to count cycle to do accurate benchmarking.

I have a core dumped on line *DEMCR = *DEMCR | 0x01000000;

What is the issue here ?

Thanks for any help. Regards

#include <stdint.h>

#include <stdio.h>

#include <stdlib.h> volatile uint32_t count = 0;

// addresses of registers

volatile uint32_t *DWT_CONTROL = (uint32_t *)0xE0001000;

volatile uint32_t *DWT_CYCCNT = (uint32_t *)0xE0001004;

volatile uint32_t *DEMCR = (uint32_t *)0xE000EDFC;

int main () { // enable the use DWT

printf("Init \n");

*DEMCR = *DEMCR | 0x01000000;

printf(" never here ? \n");

// Reset cycle counter *DWT_CYCCNT = 0; // enable cycle counter

*DWT_CONTROL = *DWT_CONTROL | 1 ;

// some code here

// number of cycles stored in count variable

count = *DWT_CYCCNT;

printf("count = %d \n",count);

return 0; }

The output is : Init Segmentation fault (core dumped)

Parents

0 br-dev over 6 years ago in reply to Jason Andrews

Hi Jason, Thanks for the help. I will give it a try based on your work on PMU with Linux Kernel in the coming days and let you know on a RPI3. In the mean time, i ran into the evaluation of the PMU versus DWT for cycle count on some ARM familly/architecture HW. It appears that PMU is now days mostly in used (PMUv3) while DWT is now too old. So the method develop in your blog should be the best choice. thanks

Here the matrix computed from the ARM doc. Three column are related to the strategy for cycle count (PMU,DWT or other). The column H/W implementation should be fill with boards name or product name. I tried to aggregate quickly the PMU versions or insert notations to give indications (when found). It's a first quick run and I am happy to received comments or to update the matrix. Feel free to send comments.

ARM family	ARM architecture	ARM core	PMU	DWT	Other	H/W Implementation	Remark
ARM11	ARMv6	ARM1136J(F)-S	N/A	N/A
	ARMv6T2	ARM1156T2(F)-S	N/A	N/A
	ARMv6Z	ARM1176JZ(F)-S	NO	NO	CCNT	RPI1B+
	ARMv6K	ARM11MPCore	N/A	N/A
Cortex-M [ARM-DOC]	ARMv6-M	Cortex-M0 [12]	N/A	N/A
		Cortex-M0+[14]	N/A	N/A
		Cortex-M1 [15]	NO	NO	?		devoted to FPGA
	ARMv7-M	Cortex-M3 [18]	NO	DWT
	ARMv7E-M	Cortex-M4 [19]	NO	DWT
	ARMv7E-M	Cortex-M7 [20]	NO	DWT
Cortex-R [ARM-DOC]	ARMv7-R	Cortex-R4 [21]	PMUVr	NO			The PMU consists of three event counting registers, one cycle counting register and 12 CP15 registers, for controlling and interrogating the counters.
		Cortex-R5 [23]	PMUVr	NO			identical to Cortex R4
		Cortex-R7 [25]	PMUvr1	NO			identical to Cortex R8
		Cortex-R8 [26]	PMUvr1	NO			identical to Cortex R7
	ARMv8-R	Cortex-R52[27]	PMUv3	NO
Cortex-A(32-bit) [ARM-DOC]	ARMv7-A	Cortex-A5 [29]	PMU ARMv7	NO			PMU for ARMv7-A and ARMv7-R
		Cortex-A7 [30]	PMUv2	NO		RPI2
		Cortex-A8 [32]	PMUva8	NO			Specific PMU Cortex
		Cortex-A9 [33]	PMUva9	NO			The Cortex-A9 PMU provides six counters to gather statistics on the operation of the processor and memory system. Each counter can count any of the 58 events available in the Cortex-A9 processor.
		Cortex-A15 [35]	PMUv2	NO
		Cortex-A17 [37]	PMUv2	NO
	ARMv8-A	Cortex-A32 [38]	PMUva35	NO			Identical to Cortex a35
Cortex-A(64-bit) [ARM-DOC]	ARMv8-A	Cortex-A35 [39]	PMUva35	NO			identical to Cortex a32
		Cortex-A53 [40]	PMUv3	NO		RPI3
		Cortex-A57 [41]	PMUv3	NO
		Cortex-A72 [44]	PMUv3	NO
		Cortex-A73 [45]	PMUv3	NO
	ARMv8.2-A	Cortex-A55 [47]	PMUv3	NO
		Cortex-A75 [49]	PMUv3	NO
		Cortex-A76 [51]	PMUv3	NO

Regards

Reply

0 br-dev over 6 years ago in reply to Jason Andrews

ARM family	ARM architecture	ARM core	PMU	DWT	Other	H/W Implementation	Remark
ARM11	ARMv6	ARM1136J(F)-S	N/A	N/A
	ARMv6T2	ARM1156T2(F)-S	N/A	N/A
	ARMv6Z	ARM1176JZ(F)-S	NO	NO	CCNT	RPI1B+
	ARMv6K	ARM11MPCore	N/A	N/A
Cortex-M [ARM-DOC]	ARMv6-M	Cortex-M0 [12]	N/A	N/A
		Cortex-M0+[14]	N/A	N/A
		Cortex-M1 [15]	NO	NO	?		devoted to FPGA
	ARMv7-M	Cortex-M3 [18]	NO	DWT
	ARMv7E-M	Cortex-M4 [19]	NO	DWT
	ARMv7E-M	Cortex-M7 [20]	NO	DWT
Cortex-R [ARM-DOC]	ARMv7-R	Cortex-R4 [21]	PMUVr	NO			The PMU consists of three event counting registers, one cycle counting register and 12 CP15 registers, for controlling and interrogating the counters.
		Cortex-R5 [23]	PMUVr	NO			identical to Cortex R4
		Cortex-R7 [25]	PMUvr1	NO			identical to Cortex R8
		Cortex-R8 [26]	PMUvr1	NO			identical to Cortex R7
	ARMv8-R	Cortex-R52[27]	PMUv3	NO
Cortex-A(32-bit) [ARM-DOC]	ARMv7-A	Cortex-A5 [29]	PMU ARMv7	NO			PMU for ARMv7-A and ARMv7-R
		Cortex-A7 [30]	PMUv2	NO		RPI2
		Cortex-A8 [32]	PMUva8	NO			Specific PMU Cortex
		Cortex-A9 [33]	PMUva9	NO			The Cortex-A9 PMU provides six counters to gather statistics on the operation of the processor and memory system. Each counter can count any of the 58 events available in the Cortex-A9 processor.
		Cortex-A15 [35]	PMUv2	NO
		Cortex-A17 [37]	PMUv2	NO
	ARMv8-A	Cortex-A32 [38]	PMUva35	NO			Identical to Cortex a35
Cortex-A(64-bit) [ARM-DOC]	ARMv8-A	Cortex-A35 [39]	PMUva35	NO			identical to Cortex a32
		Cortex-A53 [40]	PMUv3	NO		RPI3
		Cortex-A57 [41]	PMUv3	NO
		Cortex-A72 [44]	PMUv3	NO
		Cortex-A73 [45]	PMUv3	NO
	ARMv8.2-A	Cortex-A55 [47]	PMUv3	NO
		Cortex-A75 [49]	PMUv3	NO
		Cortex-A76 [51]	PMUv3	NO

Regards

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