There is a requirment for me to clean the L1 cache from Linux user space.
There is a DMAC in my SoC platform and this DMAC should read its mirco-code from L2 cache all the time.
When I need to update the DMA mirco-code located in a main-memory, I have two options: 1. pass the cache; 2. bypass the cache
The first option results in the in-coherency betweetn L1 and L2, the second option results in the in-coherency between main-memory and L2.
So the DMAC always get the dirty data in L2 cache.
Is there a system call for me to clean the L1 cache (so that the data synchronized to L2) after I update the main-memory with a cachable access?
Thanks,
Ann
Ann,
The system call you want is "cacheflush" and GNU glibc should expose this as __clear_cache() or something similar. Note that this is the only way to do cache maintenance in userspace and does imply a relatively aggressive cache maintenance in that it is intended to synchronize the instruction and data caches (for self-modifying code). As long as you're not expecting some fine-grained control over the maintenance scope (PoC or PoU) and don't mind it tinkering with the instruction cache, too, then it might do what you want.
Ta,
Matt
Hi Matt,
I would try __clear_cache() at first.
If PoC or PoU could provide fine-grained control over the maintenance scope, I prefer to it ( I am not in the use case, like self-modifying code).
Anyway, how do I implement PoC or PoU with my cortex-A9 platform?
Could you please provide more help on it?