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Help converting neon 32-bit syntax to 64-bit

lefty

Hi,

I am trying to translate a function from Neon 32-bit syntax to 64-bit. Unfortunately, I had trouble understanding the documentation

For instance, an example is this line:

vld1.32         {q0}, [%[src1]]!

translates to this:

ld1             {v0.4s}, [%[src1]], #16

what I don't understand is the "v0.4s" bit means. I suppose it somehow has to translate to the q0 register, but the logic eludes me. Anyone can help me out?

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  • 0 in reply to Simon Craske

    Thanks Simon, that's a really good answer.

    I have a follow on question. This line:

    vld1.32            {q6, q7}, [%[m]]!

    loads 8 32 - bit floats from m into Q6 and Q7. Is there a equivalent AArch64 instruction that will load 8 floats in one call?

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  • 0 in reply to Simon Craske

    Thanks Simon, that's a really good answer.

    I have a follow on question. This line:

    vld1.32            {q6, q7}, [%[m]]!

    loads 8 32 - bit floats from m into Q6 and Q7. Is there a equivalent AArch64 instruction that will load 8 floats in one call?

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