Hi. I have a question about scatter loading in multicore system (ARM-R8).
I'm working on smp in cortex-r8, and I'm going to load a binary to see if the firmware works well.
I want to place different codes in the ITCM area that exists independently for each core.
The system addresses of the ITCMs in each core are 0x100,000, 0x140000, 0x180000 and 0x1C0000 and the local addresses of the ITCMs in each core are all 0x0.
In other words, the same values are stored for core0 between 0x0-0x40000 and 0x100000-0x140000 and they are all the same for core1,2,3.
To make a binary for smp, I give each core's itcm system address as an execution region address in a single scatter file,
and I created a vector table for each core, and assigned a vector table for each core.
- example code
ITCM_CORE0_LOAD_REGION 0x100000 0x40000
{
ITCM_CORE0_EXECUTION_REGION 0x100000 0x40000
boot0.0 (vector_table, +FIRST)
}
ITCM_CORE1_LOAD_REGION 0x140000 0x40000
ITCM_CORE1_EXECUTION_REGION 0x140000 0x40000
boot1.0 (vector_table1, +FIRST)
ITCM_CORE2_LOAD_REGION 0x180000 0x40000
ITCM_CORE2_EXECUTION_REGION 0x180000 0x40000
boot2.0 (vector_table2, +FIRST)
ITCM_CORE3_LOAD_REGION 0x1C0000 0x40000
ITCM_CORE3_EXECUTION_REGION 0x1C0000 0x40000
boot3.0 (vector_table3, +FIRST)
And when I load the binary using t32, I can see that itcm contains the codes I want.
However, in the scatter file, since I set itcm execution region base address as a system address in the scatter file,, all vector tables are stored in the system address(core0: 0x100000, ..., core3: 0x1C0000).
What I want is that the vector tables in all cores are stored at 0x0 address, which is the local address of each core, so what should I do?
When I check the symbol address of the vector tables, it comes out as system address.
I don't know how to make scatter file that set itcm execution region as 0x0 with different codes for each core.
Thanks.
The (for example) 0x00140000 addresses are expected as this is defined in the scatter description file.
If you keep the load address as 0x00140000, but set the execution address to be 0x0, with the OVERLAY attribute specified, this will allow code to link as expected. Do this for each of the 4 vector tables.
... ITCM_CORE1_LOAD_REGION 0x140000 0x40000 { ITCM_CORE1_EXECUTION_REGION 0x0 OVERLAY 0x40000 { boot1.0 (vector_table1, +FIRST) } } ...
You would need to supply appropriate code to manage the overlay. Something like the following (in pseudo-code):
CPUID = get_CPUID(); memcpy(0x0, (0x100000+(CPUID*0x40000)), 0x40000);
Regards
Ronan
Thanks for replying.
I already knew about concept of overlay, and I used this option to solve the issue.
However, when I used 'overlay' option, L6258E (Entry point(0x00000000) lies in an overlaid Execution region) error occured because I set the entrypoint as 0x0 (vector table).
Perhaps this is not possible?
I am looking at the smp_primes_R8x4 example as provided with Arm Development Studio, and this has a common Vector Table for all CPUs.
Are you sure you need to use different tables? Should you instead program the interrupt controller to handle CPU specific interrupts:
https://developer.arm.com/documentation/den0013/d/Multi-core-processors/Handling-interrupts-in-an-SMP-system