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using assembly and intrinsics in C code (Arm Compiler 6)

dear arm,

Is there a more detailed document that introduces how to use assembly and intrinsics in C code?

I found a breif introduction in migration_and_compatibility_guide_v6.18. But after reading it, I still don't know how to modify the format to meet Arm Compiler 6' requirements .

The code blow shows the example in migration_and_compatibility_guide_v6.18

// __asm in Arm Compiler 5
int add(int i, int j)
{
    int res;
    __asm
    {
        ADD res, i, j
        SUB res, i, res
    }
    return res;
}

// __asm in Arm Compiler 6
int add(int i, int j)
{
    int res = 0;
    __asm
    (
        "ADD %[result], %[input_i], %[input_j] \t\n"
        "SUB %[result], %[input_i], %[result] \t\n"
        : [result] "=&r" (res)
        : [input_i] "r" (i), [input_j] "r" (j)
        );
    return res;
}

But how should I modify the code below to meet Arm Compiler 6's requirements?

MOV sum, var1, LSL #16
QADD sum, sum, temp
MOV result, sum, ASR #16
MOV zero, #0
RSB var2_inv, var2, #0

many thanks!

Parents
  • Which compiler version are you using?

    Testing with amclang 6.18, the above compiled without issue for me (both Arm and Thumb, Cortex-R4).

    Arm:
        func
            0x00000000:    e10f1000    ....    MRS      r1,APSR ; formerly CPSR
            0x00000004:    e3c11302    ....    BIC      r1,r1,#0x8000000
            0x00000008:    e128f001    ..(.    MSR      APSR_nzcvq,r1 ; formerly CPSR_f
            0x0000000c:    e2010302    ....    AND      r0,r1,#0x8000000
            0x00000010:    e12fff1e    ../.    BX       lr
            
    Thumb:
        func
            0x00000000:    f3ef8100    ....    MRS      r1,APSR ; formerly CPSR
            0x00000004:    f0216100    !..a    BIC      r1,r1,#0x8000000
            0x00000008:    f3818800    ....    MSR      APSR_nzcvq,r1 ; formerly CPSR_f
            0x0000000c:    f0016000    ...`    AND      r0,r1,#0x8000000
            0x00000010:    4770        pG      BX       lr

Reply
  • Which compiler version are you using?

    Testing with amclang 6.18, the above compiled without issue for me (both Arm and Thumb, Cortex-R4).

    Arm:
        func
            0x00000000:    e10f1000    ....    MRS      r1,APSR ; formerly CPSR
            0x00000004:    e3c11302    ....    BIC      r1,r1,#0x8000000
            0x00000008:    e128f001    ..(.    MSR      APSR_nzcvq,r1 ; formerly CPSR_f
            0x0000000c:    e2010302    ....    AND      r0,r1,#0x8000000
            0x00000010:    e12fff1e    ../.    BX       lr
            
    Thumb:
        func
            0x00000000:    f3ef8100    ....    MRS      r1,APSR ; formerly CPSR
            0x00000004:    f0216100    !..a    BIC      r1,r1,#0x8000000
            0x00000008:    f3818800    ....    MSR      APSR_nzcvq,r1 ; formerly CPSR_f
            0x0000000c:    f0016000    ...`    AND      r0,r1,#0x8000000
            0x00000010:    4770        pG      BX       lr

Children
  • I'm using armclang6.18, too.

    C:/Program Files/ArmCompilerforEmbedded6.18/bin/armclang --target=arm-arm-none-eabi -mcpu=cortex-r5 -o1 -fno-short-enums -mno-unaligned-access -mlittle-endian -g -marm @build/qogirl6_pubcp_builddir/dep/record_C_MACRO_INC.txt -c -IC:/Program Files/ArmCompilerforEmbedded6.18/include MS_Ref/source/codec/record/src/mp3_encoder/src/mp3_enc_spec_scale.c -MF build/qogirl6_pubcp_builddir/dep/record/mp3_enc_spec_scale.d.tmp -o build/qogirl6_pubcp_builddir/obj/record/mp3_enc_spec_scale.o

  • What options are specified in the file?

    @build/qogirl6_pubcp_builddir/dep/record_C_MACRO_INC.txt
    

  • These are just macro definitions and include paths. They should not affect the compilation. I'm sorry, but I don't understand why it works for me, but not for you. Can you copy the above source exactly and test? Perhaps there is a mistake in your original source?

    The following builds for me without error (both Arm and Thumb):

    armclang --version
    ...
    Arm Compiler for Embedded 6.18
    
    
    armclang -c --target=arm-arm-none-eabi -mcpu=cortex-r5 -o1 -fno-short-enums -mno-unaligned-access -mlittle-endian -g -marm cpsr.c
    armclang -c --target=arm-arm-none-eabi -mcpu=cortex-r5 -o1 -fno-short-enums -mno-unaligned-access -mlittle-endian -g -mthumb cpsr.c