How to force the branch target to be 4 byte aligned? Any compiler options to do that? I am using arm A15.

I have a tight loop listed as follow. thumb-2.

PC=0x700abdfe DISASS="MRRC     p15,#0,r0,r1,c14"

PC=0x700abe02 DISASS="SUBS     r0,r0,r2"

PC=0x700abe04 DISASS="SBC      r1,r1,r3"

PC=0x700abe08 DISASS="SUBS     r0,r0,r4"

PC=0x700abe0a DISASS="SBCS     r1,r1,r5"

PC=0x700abe0c DISASS="BCC      {pc}-0xe ; 0x700abdfe"

The target address,0x700abdfe, is not 4 byte aligned, the performance hit is huge.

How to force the branch target to be 4 byte aligned? Any compiler options to do that? I am using arm A15.