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The volatile modifier adds instructions to expand the variable to a 32-bit value (UXTB, UXTH, SXTB, SXTH).It doesn't make sense. checking code online
#include "stdint.h" struct _st { uint8_t a; volatile uint8_t b; }st; uint32_t test(uint8_t c) { uint8_t out; if(st.a > c) out = st.a; else out = st.b; return out; };
test: ldr r2, .L3 ldrb r3, [r2] //reading st.a cmp r3, r0 bhi .L2 ldrb r3, [r2, #1] //reading st.b uxtb r3, r3 // <<<<< .L2: mov r0, r3 bx lr .L3: .word .LANCHOR0 st:
Hello, thanks for your attention to the problem.I just want this business to get off the ground. You are saying that the legacy "volatile" extends to the holding register. For the safe operation of code below the load level.Okay, so ARM probably doesn't have auto-expanding boot instructions? Oops, there is "ldrsb".New piece of code, old problems: godbolt.org/.../cWza83Wrz
I am still confident that "volatile" adds extra operations that can be omitted. The Clang compiler successfully uses the correct load instructions. This means that GCC should be able to do that.In the online compiler, you can play around with the type and version of the compiler, the type of processor used, and the compilation options. Everything at once and in one place. This is more convenient than copying to the forum.It will be great if this problem is resolved.